Trench-gated MOSFETs are a class of MOSFETs in which the gate is positioned in a trench that is formed at the surface and extends into the silicon. The gate is formed in lattice-like geometric pattern which defines individual cells of the MOSFET, the pattern normally taking the form of closed polygons (squares, hexagons, etc.) or a series of interdigitated stripes or rectangles. The current flows in vertical channels which are formed adjacent to the sides of the trenches. The trenches are filled with a conductive gate material, typically doped polysilicon, which is insulated from the silicon by a dielectric layer normally consisting of silicon dioxide.
Two critical characteristics of a power MOSFET are its breakdown voltage, i.e., the voltage at which it begins to conduct current when in an off condition, and its on-resistance, i.e., its resistance to current flow when in an on condition. The on-resistance of a MOSFET generally varies directly with its cell density, since when there are more cells per unit area there is also a greater total "gate width" (around the perimeter of each cell) for the current to pass through. The breakdown voltage of a MOSFET depends primarily on the doping concentrations and locations of the source, body and drain regions in each MOSFET cell.
The MOSFET is typically formed in a lightly-doped epitaxial layer of silicon which is grown on a heavily-doped silicon substrate. The gate trenches normally extend into the epitaxial layer and are frequently rectangular, with flat bottoms bounded by corners. This configuration creates a problem in that, when the MOSFET is turned off, the electric field reaches a maximum near the corners of the gate trenches. This can lead to avalanche breakdown and impact ionization near the surface of the gate oxide, with the consequent generation of carriers. If the carriers are generated within a mean free path of the interface between the silicon and the gate oxide, they may have sufficient energy to pass through the interface and become injected into the gate oxide layer. Carriers that are able to surmount the silicon/silicon dioxide energy barrier are often referred to as "hot carriers." Hot carrier injection can ultimately damage the gate oxide layer, causing changes in threshold voltage, transconductance or on-resistance, and thereby impair or destroy the MOSFET.
U.S. Pat. No. 5,072,266 to Bulucea et al. teaches a technique of suppressing voltage breakdown near the gate by the formation, in the MOSFET cell, of a deep central body diffusion that extends below the bottom of the trenches. This deep central diffusion shapes the electric field in such a way that breakdown occurs in the bulk silicon away from the gate, in a location which prevents hot carriers from reaching the gate oxide layer. A cross-sectional view of a MOSFET in accordance with U.S. Pat. No. 5,072,266 is shown in FIG. 1A, which illustrates a MOSFET cell 10 containing a trenched gate 11, an N+ source region 12, an N+ substrate (drain) 13, an N-epitaxial layer 14, and a deep central P+ diffusion 15. Note that the lowest point of P+ diffusion 15 is below the bottom of gate 11. A plan view of MOSFET cell 10 in a conventional lattice containing other similar MOSFET cells is shown in FIG. 1B. The protective deep P+ region 15 is shown at the center of each square cell, surrounded by the N+ source region 12 and the gate 11. Four complete cells are shown in FIG. 1B. The doping of deep P+ diffusion 15 is greater than the doping of P-body 16 in the region of the channel, designated by the dashed line and reference numeral 17. As a result, the distance Y.sub.S between the gate trenches must be maintained at or above a minimum value. Otherwise, the deep P+ dopant will diffuse into the channel 17 and raise the threshold voltage V.sub.tn of the device. The value of Y.sub.s, along with the thickness of the gate, defines the cell density and helps to determine the on-resistance of the MOSFET.
To fabricate an extremely low voltage, low on-resistance power MOSFET, the dimensions of the device are generally scaled down. In particular, the cell density is increased and the epitaxial layer is made thinner, even to the point that the gate trenches may extend into the heavily-doped substrate. Such a MOSFET is illustrated as MOSFET 20 in FIG. 2A.
This creates an entirely new set of design criteria. Referring to FIG. 2A, since the corners 21C of the gate trenches 21 are surrounded by the N+ substrate 13, the electric field at these locations drops entirely across the gate oxide layer. While the formation of hot carriers in the silicon may be lower, the high electric field on the gate oxide layer may still lead to device degradation or damage. In one condition, when the gate is biased at essentially the same potential as the source and body (i.e., the device is turned off), a serious concern is that the gate oxide layer at the bottom of the trenches must support the entire voltage across the device. Compared to the embodiment of FIG. 1A, there is no epitaxial layer to absorb a portion of this voltage difference.
An equivalent circuit for MOSFET 20 is shown in FIG. 2B. Diode D.sub.DB represents the PN junction between N-epitaxial layer 14 and P-body region 22, and capacitor C.sub.GD represents the capacitor across the gate oxide layer 21A.
In the foregoing discussion it has been assumed that the MOSFET was operating in "Quadrant I", wherein (in an N-channel device) the drain is biased positive relative to the gate and the parasitic body/drain diode (represented by diode D.sub.DB) is reverse-biased. A MOSFET can also be operated in "Quadrant III" with the source biased positive with respect to the drain and the parasitic diode forward-biased. In this condition, if the gate is turned off, diode D.sub.DB presents a large (typically around 700 mV) voltage drop and stores a large number of minority carriers. This slows the diode's turn off time when the MOSFET returns to Quadrant I operation.
FIG. 3 illustrates current and voltage waveforms which illustrate the basic reverse recovery problem in conventional silicon PN diodes. During interval .DELTA.t.sub.1, the drain voltage V.sub.D is negative and the diode D.sub.DB is forward biased to some predetermined current density and forward voltage drop. During interval .DELTA.t.sub.2, as V.sub.D goes positive the current through the junction of diode D.sub.DB decreases at a predetermined slew rate dI/dt. Eventually, in interval .DELTA.t.sub.3 the polarity of the current in diode D.sub.DB reverses because its cathode has become more positive than its anode. Since the charge that was stored in diode D.sub.DB has not fully been removed, however, diode D.sub.DB continues to conduct (in a reverse direction) even though it is reverse-biased. Eventually, the stored charge will be removed (either by recombination or diffusion) and diode D.sub.DB will "recover", i.e. stop conducting. The term "reverse recovery" refers to this temporary operating condition wherein current is flowing in a device biased into an reverse polarity.
At the onset of interval .DELTA.t.sub.4, magnitude of the reverse current through diode D.sub.DB reaches a peak and begins to decline. At the same time, the reverse voltage across diode D.sub.DB begins to rise sharply. The simultaneous presence of substantial voltage and conduction current in diode D.sub.DB leads to a power loss and undesirable heating in the diode itself. In a actual application heat generated in the diode is lost power no longer available to do work in the system, and a decrease in efficiency results. The rapid change in voltage likewise produces electrical noise which can be coupled into other parts of the circuit or system. Finally, during interval .DELTA.t.sub.5, as a result of stray inductance the voltage across diode D.sub.DB overshoots the supply voltage V.sub.CC. This can lead to oscillations, noise, further power loss or even avalanche breakdown.
It would therefore be useful to provide a MOSFET that breaks down at a well-defined voltage and at a location away from the trench when it is operating in Quadrant I and that exhibits a minimal voltage drop and charge storage characteristic when it is operating in Quadrant III.